1. Field of the Invention
The present invention relates to a semiconductor device and a method of designing the semiconductor device. In particular, the invention relates to a semiconductor device including a region designed to lie on grid and a region designed to be off grid, and to a method of designing the semiconductor device.
2. Description of Related Art
In recent years, a semiconductor device manufacturing process has proceeded toward fine patterning. Further, semiconductor devices can be manufactured by transferring patterns formed on a mask to a semiconductor substrate based on lithography or other such exposure technologies. This manufacturing process has a problem in that if mask patterns are formed finely as compared with the wavelength of light for exposure, transferred patterns for manufacturing a semiconductor device are displaced from the original mask patterns due to light interference or diffraction.
In recent mask pattern formation techniques, OPC (Optical Proximity Correction) has been carried out in consideration of the light interference or diffraction. According to the OPC, a pattern shape is corrected in consideration of a distance between patterns or a combination of patterns of different shapes. For example, if a distance between adjacent patterns is small, a width of a pattern formed on a semiconductor substrate becomes small, so a mask pattern is set wider than that of design data. In other words, the OPC is intended to individually correct various combinations of patterns of different pattern shapes and pitches. If mask pattern shape and pitch can be arbitrarily set, a number of combinations of various correction types are conceivable. As a result, it takes much time to execute the OPC.
To avoid such circumstances, mask patterns used for a micromachining process are formed in accordance with on-grid layout for forming patterns based on grid points as intersections of grid lines arranged at regular intervals. The numbers of pattern pitches and widths can be reduced by forming mask patterns based on the grid point. In other words, the number of combinations for the OPC is reduced to thereby save a period necessary for the OPC. The related art regarding the on-grid layout is disclosed in Japanese Unexamined Patent Application Publication No. 2005-189683.
FIG. 6 shows a mask pattern example of the related art. In a mask pattern 100 of FIG. 6, via holes 101 are formed on grid. As shown in FIG. 6, the via holes 101 are formed in regions on and around the grid points. Here, an interval between the grid points is set to, for example, the minimum pattern pitch of the manufacturing process.
However, in the on-grid layout of the related art, the grid interval is limited to the minimum pattern pitch. In other words, patterns that could be originally formed at small intervals, should be formed based on grid points. This causes a problem that the total pattern size increases and a chip area in turn increases despite the fine patterning process.